Polarity guard

ABSTRACT

The invention relates to a polarity guard for insertion between terminals connected across a potential supply and a load means, the input polarity of which load means must be constant regardless of the polarities of the potential supply terminals. The invention has particular application to, but is by no means limited to the field of telephony wherein a transducer must often be capable of operation from a telephone line, the polarity of which is variable but the transducer requiring a constant polarity input. Typical of such a transducer is a headset amplifier for powering an electret or similar microphone in place of the traditional carbon microphone.

United States Patent [191 Moore 1 June 25, 1974 POLARITY GUARD Arthur D. Moore, Stittsville, Ontario, Canada [75] Inventor:

[73] Assignee: Microsystems lntemational Limited,

Montreal, Quebec, Canada [22] Filed: Dec. 27, 1972 [21] Appl. No.: 318,760

[30] Foreign Application Priority Data Nov. 28, 1972 Canada 157645 [52] US. Cl 307/202, 307/255, 307/262 [51] Int. Cl. H03k 17/00 [58] Field of Search 307/202, 262, 236, 127;

[56] References Cited UNITED STATES PATENTS 3,593,101 7/1971 Wassink 307/291 Primary Examiner-Rudolph V. Rolinec Assistant Examiner--B. P. Davis Attorney, Agent, or FirmE. E. Pascal 571 ABSTRACT The invention relates to a polarity guard for insertion between terminals connected across a potential supply and a load means, the input polarity of which load means must be constant regardless of the polarities of the potential supply terminals. The invention has particular application to, but is by no means limited to the field of telephony wherein a transducer must often be capable of operation from a telephone line, the polarity of which is variable but the transducer requiring a constant polarity input. Typical of such a transducer.

is a headset amplifier for powering an electret or similar microphone in place of the traditional carbon microphone.

7 Claims, 3 Drawing Figures PATENTEDJUNZS I974 Fig. l (PRIOR ART) 1 POLARITY GUARD The present invention relates to a polarity guard for insertion between terminals connected across a potential supply and a load means, the input polarity of which load means must be constant regardless of the polarities of the potential supply terminals.

The invention has particular application to, but is by no means limited to the field of telephony wherein a transducer must often be capable of operation from a telephone line, the polarity of which is variable but the transducer requiring a constant polarity input. Typical of such a transducer is a headset amplifier for powering an electret or similar microphone in place of the traditional carbon microphone.

Two basic types of polarity guard have been employed in this application one being a full-wave diode bridge rectifier and the other comprising two amplifiers connected in opposite senses, so that whichever way round the amplifiers are connected to the supply, one will always be polarized correctly. The latter of these approaches is difficult to achieve in practice, uneconomical and expensive. The full-wave diode rectifier is simple, but the voltage drop thereacross is too great for telephone use, as will hereinafter be explained.

The circuit of the present invention provides a simple and efficient means of ensuring a constant output polarity with low potential drop through the circuit and has the further advantage of being usable with either field-effect or bipolar transistors.

Thus, according to the present invention, a polarity guard comprises first and second input terminals for connection to a potential supply and first and second output terminals for connection across a load means; first, second, third and fourth transistors, said first and third transistors being of opposite conductivity type, said second and fourth transistors being of opposite conductivity type and said first and second transistors being of the same conductivity type, the control electrodes of said first and fourth transistors deriving enabling potential from said first input terminal and said second and third transistors deriving potential from said second input terminal, said first input terminal connected through said second transistor to said second output terminal and through said third transistor to said first output terminal and said second input terminal connected thorugh said first transistor to said second output terminal and through said fourth transistor to said first output terminal.

The invention will now be described further by way of example only and with reference to the accompanying drawings, wherein:

FIG. 1 is a circuit diagram of a full-wave diode bridge rectifier used as a polarity guard according to prior art;

FIG. 2 is a diagram of a polarity guard circuit according to the present invention; and

F IG. 3 is a circuit diagram of one embodiment of the present invention.

Referring now to the drawings, and in particular FIG. I, there is shown a polarity guard according to the prior art. The polarity guard is in fact a full-wave diode bridge rectifier having diodes D1 to D inclusive, input terminals A and B for connection across a potential supply and output terminals C and D for connection across a load. Terminal A is connected to the anode of D and the cathode of D The cathode of D is connected to terminal D and the anode of D is connected to terminal C. Terminal B is connected to the anode of D and the cathode of D The cathode of D is connected to terminal D and the anode of D is connected to terminal C.

If the potential appearing at terminal A is positive, D, conducts and the potential appearing at terminal D is the same as at terminal A minus one diode drop. Similarly, diode D will conduct since terminal B is negative, and terminal C will attain the same potential as terminal B, minus a diode drop. If the input polarities are reversed, diodes D and D will conduct instead of D and D respectively and the result will be terminal D positive and terminal C negative. Thus, the polarities of terminals C and D are the same, regardless of the polarities of terminals A and B. However, in each case, the potential across C and D is two diode drops less thanthat across A and B and, particularly in telephone applications, this could be a substantial percentage loss in the available output voltage.

The basic circuit of the present invention is shown in FIG. 2. It comprises input and output terminals A, B and C, D, respectively input terminal A being connected to output terminal D through a transistor 0;; and input terminal B connected to output terminal C through a transistor 0, Q; and 0;; being of opposite conductivity type. Terminal A is connected to terminal C through transistor Q and terminal B is connected to terminal D through transistor Q4 Q2 and 0., being of opposite conductivity type. As stated above, transistors Q, to Q inclusive may be either field-effect or bipolar transistors, depending upon the environment to which the polarity guard is applied. Suppose it is required that terminal D always be positive and terminal C always be negative. Let terminal A be positive and terminal B be negative. Thus it is required that transistors Q1 and 0;, both be enabled to make the A D and B C connections. Now let terminal A be negative and terminal B be positive. Now it is required that transistors Q2 and Q, be enabled to make the A C and B D connections. This is achieved by making Q and Q of the same conductivity type i.e. both conducting current to or from terminal C, depending upon the required polarity thereof but selectively enabled by tying the control electrode of O to terminal A and the control electrode of O to terminal B. Thus if terminal C is required to be negative, the current flow through Q, or Q would be from A to C or B to C, respectively depending upon which of Q; or O is enabled. Thus Q, and 02 both require positive enabling potentials and if terminal A is positive 0, will be enabled, completing the B C connection and if terminal B is positive Q will be enabled, completing the A C connection. Thus terminal C is unconditionally negative.

Transistors Q and Q, are connected in precisely analogous fashion to ensure the unconditionally positive polarity of terminal D. Clearly, to enable the transistors, the minimum potential applied is the enabling potential, which forfield-effect devices is V and for bipolar transistors is V However, when the appropriate transistors are enabled, the only series drop is across the input and output electrodes of the transistors which is considerably smaller than the corresponding drop across the conventional diode rectifier bridge. Also, by connecting the control electrodes of the transistors as shown, the appropriate enabling potentials are automatically applied, dependent upon the input terminal polarities, and the need for separate logic control circuitry is obviated.

FIG. 3 shows an embodiment of the circuit of FIG. 2, using bipolar transistors.

The circuit comprises input terminals A and B adapted for connection to a power-supply. Terminal A is connected through first resistor R to the base electrode of a transistor T The emitter of T is connected to terminal B.

Terminal A is also connected to the emitter electrode of a transistor T the collector of which is connected to a terminal C. The base electrode of T is connected through a second resistor R to terminal B.

Terminal B is connected through third resistor R to the base electrode of a transistor T The emitter of T is connected to terminal A.

Terminal B is also connected to the emitter electrode of a transistor T the collector of which is connected to a terminal D. The base electrode of T is connected through a fourth resistor R to terminal A.

Transistors T and T are both NPN type and T and T are PNP type. Suppose now a positive potential is applied to terminal A. This potential is applied to the base of T through first resistor R, and through fourth resistor R to the base of T Now, since T is a PNP transistor, positive potential at its base will not cause it to conduct. T,, however, conducts. Since a positive potential is applied to terminal A, a negative potential is applied to terminal B. Since T is enabled, a negative potential obviously appears at terminal C. The negative potential at terminal B is also applied to the base of T through R and the base of T through T Since T is an PNP type, the negative terminal at its base electrode causes it to conduct and a positive potential therefore appears at output terminal D.

Consider, now, the case where terminal A is negative and terminal B is positive. Now, instead of T, and T conducting, T and T conduct, and the potential polarity of terminal B is therefore passed to terminal D i.e., positive. Conversely, terminal C is negative. Thus, terminal D must be positive and terminal C negative, regardles of the polarity of terminals A and B.

For this circuit, the total series voltage drop is across two collector-emitter junctions and is, therefore, cEsAT of 1) (VCE'SAT of 3) or (VCESAT of 2) (VCESAT of 4)- Within practical limitations these drops may be made almost negligible and using conventional bipolar silicon planar technology and with suitable device design, the total drop in the circuit may be as low as 150mv.

Various alternatives and modifications to the embodiments disclosed herein will be readily apparent to those skilled in the art without departing from the spirit and scope of the invention as described by the disclosure and defined by the claims appended hereto.

What is claimed is:

l. A polarity guard having first and second input terminals for connection to a potential supply, and first and second output terminals for connection across a load, said polarity guard characterized by first, second, third and fourth transistors, said first and second transistors being of one conductivity type, and said third and fourth transistors being of another conductivity type, the control electrodes of said first and fourth transistors being connected via first and fourth resistors respectively to said first input terminal and the control electrodes of said second and third transistors being connected via second and third resistors respectively to said second input terminal, said first input terminal being connected through said second transistors to said second output terminaland through said third transistors to said first output terminal and said second input terminal being connected through said first transistor to said second output terminal and through said fourth transistor to said first output terminal.

2. The polarity guard as defined in claim 1 characterized in that said first, second, third, and fourth transistors are bipolar transistors, the control electrodes of said first, second, third and fourth transistors being the base electrodes of said first, second, third and fourth transistors.

3. The polarity guard as defined in claim 2 characterized in that the first and second transistors are n.p.n. bipolar transistors and the third and fourth transistors are p.n.p. bipolar transistors.

4. The polarity guard as defined in claim 1 characterized in that the first and second transistors are n.p.n. bipolar transistors, the third and fourth transistors are p.n.p. bipolar transistors, the collector electrodes of the second and fourth transistors being respectively connected to the second and first output terminals, and the emitter electrodes of the first and third transistors being respectively connected to said second and first input terminals.

5. The polarity guard as defined in claim 2 characterized in that the first and second transistors are n.p.n. bipolar transistors, the third and fourth transistors ar p.n.p. bipolar transistors, the collector electrodes of the second and fourth transistors being respectively connected to the second and first output terminals, and the emitter electrodes of the first and third transistors being respectively connected to said second and first input terminals.

6. The polarity guard as defined in claim 1 characterized in that the first and second transistors are N- channel enhancement type field effect transistors and the third and fourth transistors are P-channel enhancement type field effect transistors.

7. The polarity guard as defined in claim 6 characterized in that the control electrodes of said first, second, third and fourth field effect transistors are the gate electrodes of said field effect transistors. 

1. A polarity guard having first and second input terminals for connection to a potential supply, and first and second output terminals for connection across a load, said pOlarity guard characterized by first, second, third and fourth transistors, said first and second transistors being of one conductivity type, and said third and fourth transistors being of another conductivity type, the control electrodes of said first and fourth transistors being connected via first and fourth resistors respectively to said first input terminal and the control electrodes of said second and third transistors being connected via second and third resistors respectively to said second input terminal, said first input terminal being connected through said second transistors to said second output terminal and through said third transistors to said first output terminal and said second input terminal being connected through said first transistor to said second output terminal and through said fourth transistor to said first output terminal.
 2. The polarity guard as defined in claim 1 characterized in that said first, second, third, and fourth transistors are bipolar transistors, the control electrodes of said first, second, third and fourth transistors being the base electrodes of said first, second, third and fourth transistors.
 3. The polarity guard as defined in claim 2 characterized in that the first and second transistors are n.p.n. bipolar transistors and the third and fourth transistors are p.n.p. bipolar transistors.
 4. The polarity guard as defined in claim 1 characterized in that the first and second transistors are n.p.n. bipolar transistors, the third and fourth transistors are p.n.p. bipolar transistors, the collector electrodes of the second and fourth transistors being respectively connected to the second and first output terminals, and the emitter electrodes of the first and third transistors being respectively connected to said second and first input terminals.
 5. The polarity guard as defined in claim 2 characterized in that the first and second transistors are n.p.n. bipolar transistors, the third and fourth transistors ar p.n.p. bipolar transistors, the collector electrodes of the second and fourth transistors being respectively connected to the second and first output terminals, and the emitter electrodes of the first and third transistors being respectively connected to said second and first input terminals.
 6. The polarity guard as defined in claim 1 characterized in that the first and second transistors are N-channel enhancement type field effect transistors and the third and fourth transistors are P-channel enhancement type field effect transistors.
 7. The polarity guard as defined in claim 6 characterized in that the control electrodes of said first, second, third and fourth field effect transistors are the gate electrodes of said field effect transistors. 